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Recent content by jgrigo

  1. J

    Integers in VHDL, what happens to natural range 0 to 1000 int counter if never Rst...

    For an integer defined with range 0 to 1000, and if the integer is an incrementing counter. What happens if the signal that resets an integer counter never goes active and the integer counter does not have a clamp? How does the synthesizer handle an integer counter that is attempting to go...
  2. J

    PATA NANDrive with built in NAND Controler to I/F w/FPGA -- need help

    Quick FYI, I did a search and did come up with some info, but the info is years old. Anyway, I am currently looking at the newest technology trends pertaining to non-volitile memory since we are looking to designing a small form factor PCB that can record TDM data at >20Mbytes/sec, >8Gbytes...

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