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I meant a Virtex 7. Xilinx is slowly stopping support for the old ISE Design Suite, so I am trying to learn the new Vivado software.
The choices have a series of HSLVDCI, HSTL, HSUL, LVCMOS, LVDCI, and SSTL.
But they all appear to be either 1.5V or 1.8V.
I am just creating a new set of I/O...
Yes, I do plan on using other parts of the FPGA to communicate with each other.
When I try to set VCCO to a certain voltage, there only appears to be LVCMOS18, and I am unable to find LVCMOS33.
So when doing this, I would set one set of I/O ports to 1.8V and another set of I/O ports to 3.3V...
Hello,
I'm fairly new to FPGA design, but currently I am using two different FPGA's, one running at 3.3V and another running at 1.8V.
I would like to use another FPGA to connect both the 3.3V and 1.8V together so that they can communicate with one another.
If i use Vivado, should I just use...
I need to review a pinout list for parts in OrCAD to make sure that the correct pins and pin headers are assigned together.
Doing this for parts that have 1000+ pins can be very tedious, and I am going to attempt to write a script to review the pin out list in OrCAD to the given pin out list...
I haven't found any good ones as of yet, but I'll just keep doing more research.
I wrote the code for an encoder going from Thermometer code( 7 downto 0) -> one hot -> binary (3 downto 0).
Xilinx compiles it and uses 4 LUT's to make the encoder. I was wondering if there were any other...
Ha, I guess its common sense on my part.
Now I just need to somehow try to get the delays between the taps to be more consistent delays in between.
I guess this is where I have to start reading all those research papers.
Okay, I figured out the problem above, but now the delays are all tweaked.
From the output of the XOR gate to the DFF, all the delays appear to be in order with similar delay signals:
( the delay in the middle is the transition from carry1 to carry2)
However, once the output of the DFF...
Okay the problem I'm having now is that the COUT is not being recognized. Therefore, the second carry4 chain is not being used and receiving "XXXX"
I'm not sure if I have to manually route each MUX within the carry4, or if it is because the optimization tool is taking it away?
My code for...
Yes, I placed my DFF adjacent to the carry4 chain.
If I wanted to have 8 delays using 2 carry4's would I need to constrain the second carry4 chain in the UCF file so that the carryout of the first carry4 can be the carry in for the second carry4?
here is an example of my DFF's:
Okay, now I have gotten the carry4 chain to connect, but the delays are off.
I assumed that it would become '1' from 0-3, but it may be the delay from the routing or something else?
Any help would be appreciated
Okay, I will try out some more new things.
I'm sticking with the virtex-6 as there is much more information for the virtex series.
The wave union approach was mainly to calibrate the delays according to PVT, but that is the least of my concerns as of now.
Do you know the names of the primitives?
Or do I need to create a UCF file to keep those connections in certain cell blocks.
And it looks like I have a long project ahead of me. I have started to learn vhdl the past few weeks so I am still learning both VHDL and things about the TDC.
I've tried using FDR, but it will connect to some of the cells to the left.
And yes, I am trying to use this to create the delay element for the TDC, it is just a lot more time consuming than I had planned.
Do primitives even exist for those DFF's adjacent to the carry4?
I still don't know what the name of the DFF's are to instantiate them.
I want to connect the outputs from the carry block to the D inputs of the DFF to the right of the carry block as shown:
I am currently trying to connect the one slice of a carry4 to the DFF adjacent to it.
This will be used as a delay element to to output a thermometer code.
I can't seem to get them to connect as I don't know what the primitive for the DFF's are.
I tried using FDCE and that wired it to a...
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