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Recent content by Jet_wu

  1. J

    Why marker shifts as we zoom in or out in Cadence IC5141?

    Cadence IC5141 are there full tools in ic5141? Or does it need isr
  2. J

    [help] on-chip crystal oscillator design

    you'd better change the timestep to 0.5n and reduce the rise time of vdd. There is no need to run so much time. add ".opt accurate"
  3. J

    [help] on-chip crystal oscillator design

    increase the openloop gain when 0 phase shift set the initial current of L in crystal model to speed up the tran simulation.
  4. J

    question on analog artist

    what about verilog-A models output . I just know that the artist integrates the verilog-A and recognizes it automatically.
  5. J

    How do you take bulk effect into accout?

    edaboard spice acout I think that it should be considered with the current in the bulk. If it is little, the resistance could be canceled.
  6. J

    how to simulation switch Cap filter in hspice

    There is some example about it in the second version of "CMOS Analog circuit design" written by Allen
  7. J

    Does post-layout simulation make design more accurate?

    When there is great different between the pre-simulation and post-simulation, which could doubt among the circuit design, layout design, and the models? 8)
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