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Recent content by jessilen

  1. J

    ALU 4 bit data multiplexer

    Hello Everyone, I got this assignment as attached, but I am completely useless in Verilog. The codes that I have so far: Template module ALU_4bit_template(clock_50,key0,key1,hex5,hex4,sw0,sw1,sw2,sw3,sw4,sw5,sw6,led_clk_reg,led_clr, led_sw, led_add_cout, led_sub_cout); //(don't change) //...

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