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Recent content by jerrymelb

  1. J

    switching capacitors for VCO (Help!)

    Hi, everyone. Dose any one know how to build an array of switching capacitors for high frequency VCO? Or any paper I could learn from? I tried some transistor models, its on/off states are not clearly seperated. Thanks in advance! Regards Jerry
  2. J

    Any layout short course in Australia?

    Swathi That would be great! Could you help me? So much I want to learn. Thanks Jerry
  3. J

    Any layout short course in Australia?

    Hi, all Does anyone know that is there any layout short course in Australia? Or any company in Australia does layout? I would like to attend a short course or visit a company to gain some experiences. Regards! Jerry
  4. J

    anyone used ASITIC to design inductor?

    My collegue designed 50pH inductor using ASITIC on 0.13um CMOS. So the answer is, should be fine.
  5. J

    Is Assura good enough for 0.13/0.18um CMOS verification?

    I use Assura for 0.13 technology, so far, I don't see anything bad.
  6. J

    transfer from 0.18um to 0.13um, what are different?

    The biggest difference should be the design rule, I think.
  7. J

    IBM 0.13um CMOS layout question.

    ibm cmos 13 course HI, Franck 1) It is a LVS problem with my nfet. It says the B-terminal should connect to GND which I think I have. 2) No, there is no nwell for this. 3) Yes, I try to LVS this nfet only in a test case cell. It's a simple inverter. 4) Yes, I tried this method too, didn't...
  8. J

    IBM 0.13um CMOS layout question.

    ayout 0.13 um Thanks1 But there is no PIMP or NIMP in the library. I have used nTiedown (active, cont, M1) and pTiedown, they didn't work. Jerry
  9. J

    IBM 0.13um CMOS layout question.

    edaboard + 0.13um Franck. thanks for that Here is the probelm, I don't know which one is PTAP in cmrf8sf. Subc is substrate contact and should be the one, but unfortunately, it dosen't work. Cheers Jerry
  10. J

    IBM 0.13um CMOS layout question.

    contact substrat ibm 0.13 Hi, everyone Did I make myself clear? Could anyone help me, please? Thanks a lot!
  11. J

    IBM 0.13um CMOS layout question.

    cmrf8sf Hi, has anyone used cmrf8sf tech before? I am stucked with nfet transistor (nfet_inh and nfet_rf are okay). How can I connect the B-terminal to ground in layout? Do I use nTiedown? I have tried subc, nTiedown, not working. Any suggestions? Thanks!
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