Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by jdb2

  1. J

    Synthesis of Integer in Verilog

    This is actually not true -- Verilog integers are 4-state types. It seems I got "integer" mixed up with SystemVerilog's 2-state "int" type. jdb2
  2. J

    Synthesis of Integer in Verilog

    I thought the OP wanted a 32-bit counter. His original code was using a 32-bit integer but limiting its range to 0 through 255. Perhaps I mistook the OP's intentions? Regards, jdb2
  3. J

    Synthesis of Integer in Verilog

    I didn't say they aren't synthezisable; I said they "might" not be synthesizeable. I've never had many occasions to use Verilog integers for synthesis -- I use them mainly for eg. for loop variables to generate code. I thought I remember having problems with Verilog integers with regard to...
  4. J

    Synthesis of Integer in Verilog

    There are several problems with your code. First, you're using the integer type, which isn't always synthesizable -- you should use a reg type or logic type ( as it appears you code is SystemVerilog from the implicit continuous assignment ) for the counter variable ( Also, the "integer" data...
  5. J

    [SOLVED] syntax error generate statement

    The first problem with your code is that you're using the reserved keyword "genvar" for the module name -- you'll have to use a different name. The second problem is the lack of a name for the for loop block in the generate statement. Furthermore the expression "xor g1(z1(i),x(i),y(i));" is a...
See more

Part and Inventory Search

Back
Top