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Recent content by jcchan

  1. J

    Why do we need a start up circuit for this bandgap?

    Re: bandgap start up thak you, it is very usefully to me.
  2. J

    What is the maximum current that can be drawn through a USB connection?

    Re: USB The max operation is 500ma.
  3. J

    verilog a code for divide by n

    divide in verilog module Divide_N ( reset, clk, enable, n, clk_out ); input clk; input reset; input enable; input [7:0] n; output clk_out; wire [7:0] m; wire dbn_en; reg [7:0] count; reg out1; reg out2; wire out...
  4. J

    Generate 27 MHz clock from a 40 MHz input clock on a FPGA

    Re: Generate 27 MHz clock from a 40 MHz input clock on a FPG To use PLL macro in FPGA
  5. J

    Looking for info on flash memory controller

    Re: memory controller thanks a lot!!!!
  6. J

    How to costraint clock generated by combination logic in DC?

    Re: How to costraint clock generated by combination logic in i think option 2 is best for constraint.
  7. J

    digital delay locked loop codes

    delay locked loop fpga vhdl pls to refer to the TI 74ls297, it is digital pll structure.
  8. J

    How to add pull-up /pull-down resistor for FPGA's IO ports

    pullup fpga thanks, it works when use pull in constarint file.
  9. J

    How to generate a two phase differential non-overlapping clock?

    Re: two phase clock to use SR latch and delay cell.
  10. J

    How to use FPGA to control ATA/ATAPI-6 hard disk ?

    Re: ATA/ATAPI-6 To visit the website www.t13.org.
  11. J

    IR-reducing problem in Magma software

    Re: IR-drop problem You can make width of power ring bigger.
  12. J

    Whats the maximum clk for spartan3 FPGA?

    Re: clk of fpga The Max clok is according to your degign. More complexities, the lower clk you get.
  13. J

    How to connect i/o DC supply voltage?

    Re: connect power to i/o pad There must have two power pad, one is high voltage and another is low voltage power pad. The IO ring power is connected to high voltage power pad and core power is connected to low voltage power pad. A power cut cell must be placed between high voltage power ring...
  14. J

    what will happen if we dont use filler cells?

    The filler cell is used to connect well and power line of standard cell and to do this is good for yield.
  15. J

    What is the purpose of minimum area design rules

    Re: Tapping for Latch up? The easy way to check latch up path is p(vdd)-n-p-n(gnd).
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