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Well that, and then annotating with SDF so that it has post-layout timing information.
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There is, but for pure digital, it's typically post-layout gate-level with SDF based on extracted RC, rather than transistor level simulation.
You can do transistor level simulation for...
If you know roughly how frequently FFs and gates toggle for a particular design, you can multiply that factor by the number of gates times the power consumption for the average gate, for a very coarse estimate. But it's very easy to be orders of magnitude out.
Verify > Extract uses Diva for DRC, and can't use Calibre DRC rules. So you either need a different rule deck or run Calibre. (Which would be Calibre > Run nmDRC if you have it installed and setup).
Yes, you need to use a VCD file, otherwise the toggle count used for the power estimation is just a fixed value, and is unlikely to be the same as in your design. As dynamic power is proportion to the amount of toggling, this can result in widely inaccurate power estimates. You can read a VCD...
There's an open source GPU here: https://github.com/VerticalResearchGroup/miaow/wiki/Architecture-Overview - so you can even take a look at the source code if you want.
Have a look at the hotchips archive if you want to see details for lots of different types of processors...
Perhaps a silly question, but did you just try synthesizing assign product = multiplicand * multiplier? Design compiler has some fairly decent implementations if you have a DesignWare license. (Make sure you do set_app_var synthetic_library "dw_foundation.sldb")...
2) Yes for the cheaper licenses. No for the full licenses. But quality of results and runtime will degrade if you try to P&R too many at a time.
4) x64 / Linux
5) No
size_only is perhaps better than dont_touch if you want to preserve something. (You don't necessarily even need to use this will manually instanced clock gates).
Not sure what you mean by a generated clock in this context.
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