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Re: how to add two voltage signals without cap in analog des
Hello,
I have few questions for you.
1. what is the operating frequency? and do both the signals have same frequency.
Do you mean literally adding the signals to each other under all conditions and are the signals always gonna be in...
it would be a lot easier if u can post a pic of ur test bench.
may be , setting up initial conditions at important nodes such as the output of charge pump might help. Do u have individual verilog blocks for each element in the PLL or the whole PLL as such?
another suggestion would be to check...
what is repeaters
if u r trying to use repeaters in a long transmission line, u can use adequately sized identical inverters. if ur question was on designing a buffer, u can use 2 inverters together to make it look like a non inverting buffer.
if u wanna minimize a critical path delay, u may...
First, I would like to know what was the test bench setup and how pure was the input signal. The distortion in the input signal in addition to improper reference for the ADC will definitely make the ADC testing bad and make the measurements look worse.
The above conditions are true if ur ADC...
Re: how to mantain a constant gm in a resistive loaded diff
Hi LvW,
Thanks a lot for the reply. I perfectly understand what you say. We can indeed sense everything and regulate other parameters with ofcourse a few drawbacks. There is no free lunch.
I believe I should explain the reason why...
Hi guys...
I would like to know about the variation of gm with temperature and ways to compensate for it. In a resistive loaded diff pair, if the gm reduces with temperature, is there a circuit technique that can sense it and maintain the gm fairly constant?
Suggestions on this would be very...
Hi,
There is a 3 stage equalizer on the receiver side operating at 5Gb/s. The gain of the individual stages and hence the total gain of the equalizer varies with temperature from -25 to 125 ( negative temp co). Each stage comprises of a Resistive loaded Diff pair( Resistors are used to ensure...
could u plz explain more on the architecture u have used. is it SC or CT?, no. of quantizer bits?. is this a post layout simulation? are u considering parasitics also while simulating? wat process and supply voltage u r working on?wat kind of dac are u using in the feedback?plz explain in detail...
Re: sigma delta output
the digital output of a sd mod with dc inut will be alternate 1's and 0's whose avg tend to be the dc input voltage. you can better understand this if u can run an fft on the output of the sd modulator with a dc input. the fft shud have the signal component at dc (0 hz)...
Re: Maybe silly question about first-order sigma-delta modul
Hi,
As far as i know, the excess loop delay is an important factor to be considered in a continuous time SD modulator. Excess loop delay is the delay in the rise time of the sampling clock to the ouptu of the dac in the feedback...
delta loop design
Hi,
if you simulate the DS toolbox and get the value of coefficients, the value of g1 is very small in the order of 10^-4 and can usually be neglected for the above structures u mentioned.
no convergence in operating point +hspice
try using the following .options
I didnt have time to pick out the options. But just use this in ur sim and let me know if u still have probs.
.OP ALL
.OPTION ACCT NODE OPTS LIST LIMTIM=50
+ GMIN=1.00E-12 RELTOL=0.01 ABSTOL=1.00E-12
+...
allocating more memory +hspice
Hi,
I am trying to simulate a complex circuit in hspice and I get the following error in the version 2006 and before:
**error** the memory request exceeds the current available space.
# memory which has been allocated = 1098404 kbytes
#...
folded cascode amplifier design
Do you mean Allen hasting's book?
I just wanted to know how to design the bias circuit for a cascode stack? 2 stacks of PMOS and 2 stacks of NMOS.
I jus wanted to know the basic procedure for that.
folded cascode design
Hi all,
I am new to analog design and I am currently designing an Nmos input folded cascode amplifier. I have the following specs to meet at Vdd 2.7V and 0.35u technology:
can use an ideal current source of 5uA which can be mirrored accordingly.
Aol >50dB
swing = 2 V...
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