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I am studying the process of aging in CMOS. I have seen the concept of "charge trapping" multiple times. Can someone explain this concept, and how it affects switching speed?
-Thanks
I created one library in modelsim where I compiled multiple desgins. Now, I would like to re-use those circuits in another library as they are instantiated in a top module. Is it possible to link that library into new libraries without the the need of compiling the circuits again?
-Francisco
A workaround may be creating top script (main.csh) where you can pass arguments when you call it ($1, $2). Consequently, this script will modify your script (myScript.tcl), and at the end you just call prime time automatically by means of the main.csh
- generate empty files and then wonder why it doesn't work
Does it mean there is something missing in my script to generate the file properly, wondering what is it?
- generate a valid file but with a hierarchy mismatch. this happens because the simulation environment usually has a testbench...
I want to execute GLS with a timing model using PrimeTime. After generating the netlist, I successfully ran GLS with ModelSim using the .sdf file given by Synopsys DC (cmd: write_sdf sdf_dc.sdf). However, the problem arises when using the .sdf file generated by Prime Time with a timing model as...
I am using the principles of approximate computing in arithmetic circuits for research purpose. For bigger arithmethic operands I am using the designware library as part of small sub-designs for the approximate multiplier. Planning to synthesize only that component, but later I would like to...
I am doing research at component level, and basically would like to synthesize new circuits at architecture level. However, would like to have an efficient method to substitute all the arithmethic circuits automatically in all the RTL code for evaluation purpose. Wondering if there is a way to...
I know that I have to use the netlist in PrimeTime Px for power estimation, but Do I need to use the netlist file in Modelsim to generate the VCD file, or the original code (given to DesignCompiler) is enough? I try both methods, and definitively the simulation with the original code is much...
Would like to generate VCD files for multiples circuits in Modelsim in order to estimate power with PrimeTime. I automatized the process of synthesis in Design Compiler using "dc_shell -f myScript.tcl". Is there a similar way to do this in Modelsim without the need of opennig the GUI?
Francisco.
Completely agree with that. In my own experience, HLS is pretty good with datapaths in terms of design exploration as you can easily trade-off performance and area. For instance, re-using arithmethic units to process a given application.
Hello everyone,
After generating the netlist of my circuit with Design Compiler, I proceed to generate the VCd file in modelsim in order to obtain the power estimation with Prime Time PX. My problem happens when I generate the vcd file as I am running out of space in the HDD. My question is...
I do believe that HLS is more efficient in terms of Datapath design, and also it would give much better flexibility to explore multiple desigs. Considering that, yes I am looking for something that can help with that in less time, even if I am not an expert with HDL.
Hello,
My goal is to synthesize RTL in any specific technology library using Design Compiler. However, as you know the implementation of RTL using HDL consumes significant time. Therefore, I would like to explore HLS. I 've been reading about Vivado HLS which has a free version for students...
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