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Re: trobled with the system parameter design of fractional-p
the bandwith variation is just one of my problems.
the huge area requred by the cap in the lpf also makes me headache. since the bandwith is set to be 50hz, the cap is as big as nF!
can active filter solve this problem? what is the...
Re: trobled with the system parameter design of fractional-p
aProgrammer:
thx for ur suggestion
but the spec requires N varies from 1 to 128. we tried to vary Icp with N, but it also bring a lot of problems.
i am really troubled
we wanna design a fractional pll with ring oscillator.
the input frequency is from 5M to 50M, and we set the bandwith to be 50khz, the segma-delta modulator is 3th order. the current ICP is varying with the N which varies from 1 to 128
the troble we meet is by calculation the Cs in the LPF is...
i am new to design fn pll.and i wrote some verilog coeds of the segma-delta modulation.
but the result is wrong,i guess,but not sure
how to know the result right or wrong?
i post my code here,pls heip point out the mistakes if there are.
//define constant
`define add1 10
`define add2 10...
fractional-n pll clk generator
i need a clock whose frequency step is only 100khz or even less
i know in rf system there are fractional-n structure plls which can make the frequency step very small, but i never hear about fractional-n pll used as the clock generator.
can i use a fractional-n...
hello all
recently i am dealing with a vco, i paste it on the web, can u see?
it is a delay cell, vc is the contral voltage of the vco. i think most of u are familiar with this kind of vco.
my QUESTION is : why the gate of MNC be connected to vdd, to operate in triode region?
a paper says...
can i explain it in this way？
the transer function of the vco noise to the output is high-pass ,do u agree with me? so the bandwidth is the bigger ,the better
because the Kvco is proportional to bandwidth, in my opinion bigger kvco does restrict the noise caused by the vco
please point out any...
i was asked the question when i was interviewed. my answer is for the noise of the input signal, Kvco the smaller ,the better; for noise of vco, the answer is converse
it that right ?
thx
Re: Kvco is too large?
hard to realize it?
i want to make a pll as a clock frequency multiplier for HDMI1.3
the data clock is 25M to 340Mhz, and the pll is used to 5 times the clock frequency
so how can i do it
thx
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