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Yes, I see this issue and don't see an obvious solution within my existing framework as the problem is a recursive one.
How does one prove an asynchronous state machine is safe?
Given that fin should be able to go as fast as the logic will allow (well over 100MHz), are there any standard...
Thanks for your reply.
Could you give me an example of how this would work? In the case of the code above, the asynchronous input (signal whose frequency is to be measured) runs many times faster than any synchronous clock in the system. The gate clock runs at 1 to 100 Hz, but fin can run at...
Hi,
I've written some code for a CPLD to perform the functions of a frequency counter. The code is working fine, but I'm getting some warnings about inferred latches. I understand why the compiler is generating the latches, but I'm wondering if there is a better way to do it. Here is the...
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