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i just declare a variable, then value is given to that variable . For example reg a<= 100; .i need to find the address of that variable "a" which contain 100 using verilog.
is there any option to produce 500 ms delay without using counter in verilog. because counter needs clock input. Iam unable to use clock as input signal.
It is for actual hardware. Iam using psoc 3. 1000 ms corresponds to 1 HZ. so iam using counter that counts up to 1000. In it there was a high pulse upto 500 and remaining 500 as low pulse. i don't know this method is correct or not. for simulation we use delay such as( #num).
for example # 5 a=b...
I wanted to implement 1 HZ square wave in verilog with out giving system clock signal as input.in which first 500 ms the signal should be high,and remaining 500 ms the clock should be low. i write the delay program by using my logic but clock is always high
my code
module clkgeneration2...
i wanted to implement i2c communication with psoc by using verilog . As a part of this i wanted to generate SCL clocks signal . i know SCL timing diagram and also what changes happened to reading and writing operation on SCL . how to implement SCL signals by using this data . If anyone knows...
hello everyone
Iam using PSOC . PSOC board support verilog. i wanted to implement clock generator in this board. anyone please help me .how to implement this .
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