Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Tool introduce timing margins provided by the user for modelling various behaviors which one could see in real silicon. At the DC stage we specify larger number for uncertainty to account these.We always provide the tight timing margins for the DC Tool to do a better job in optimizing the...
Hi,
Please make sure that you have loaded all the dbs that are required in the design for the Memories,Pads etc ...
compile_ultra fails if the design is not linked correctly.
Make sure the Link report is clean and returns 1, Without any warnings.
Regards
A Track is generally used to define the height of a standard cell .So a 9 Track cell will be taller than the a 7 Track Cell. As the routing space horizontally available over the 9 Track is more compared to 7 Track , former will be faster (better driving capacity) and consumes more space than...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
