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Recent content by jas2005

  1. J

    interpretation of PLL simulation results

    Hello I used time tolerance for cross event equal to 1 ps. But ok I'll make this tolerance stiffer. Sorry, maybe I didn't write it clearly enough. I made two transient analysis with added instance, which helped to measure close loop phase noise of a PLL circuit (with loop bandwidth 100kHz)...
  2. J

    interpretation of PLL simulation results

    Hello I have one more question. I made the mentioned simulation for circuit with ideal (written in verilogA) frequency divider and with the treansistor level one. As a reference signal I was using the sinosuidal source (3.9 MHz) with 50 ps as a falling and rising time. I noticed that when I...
  3. J

    interpretation of PLL simulation results

    Thanks for the answer. I observe Phase noise calculated from transient analysis. The part of user guide: If the PLL noise performance is of interest, add a freq_meter instance to the test bench. This instance measures the periods of VCO output in response to rise cross events and writes the...
  4. J

    interpretation of PLL simulation results

    measuring pll loop bandwidth graph Hello I made a simulation of the PLL. Its parameters are: reference freq: 3.9 mHz output freq in lock: about 308 MHz freq divider ratio: 79 Charge pump current: 25uA I used three state PDF/CP and 2nd order passive loop filter. I simulated close loop phase...
  5. J

    About PLL phase-noise and tran simulation with spectre

    pss simulation sin wave autonomous Hello Actually I overlooked one thing. I said that pss analysis hung-up, but I noticed that the convNorm was quite big like 27.2e+03. So I checked again. In fact the analysis were making loops and after long time just sttoped. So there is a problem with...
  6. J

    About PLL phase-noise and tran simulation with spectre

    spectrerf hidden state problem Hello I was performing the pss and pnoise simulation but some problems occured. Let me describe my system. I'm making PLL which consists: Reference voltage (square wave-vpulse): 4MHz PFD/CP: 3 state, transitor level Loop Filter: second order (R+C) || C VCO...
  7. J

    About PLL phase-noise and tran simulation with spectre

    +pll +spice +noise Hi I'm tring to make the simulation of PLL with two ideal blocks: VCO and Divider (it'll be faster then full system simulation, which I'm going to make at the end when everything will be ready). I used voltage domain Divider from Cadence example. But during the pss analysis...
  8. J

    About PLL phase-noise and tran simulation with spectre

    periodic steady state pll spectre Hi gaom9 How did you solve your 1st problem:
  9. J

    frequecy divider of digital signals

    it's not a problem with detecting egdes (there is even such block in simulink) and delaying signal after that. My question is: can I find a described in first post, block in Simulink? If not, how to build it? === The scheme is in the picture. I used counting both edges in order to obtain odd...
  10. J

    frequecy divider of digital signals

    Hi I'm trying to build a simple model of frequency divider in simulink. I used counter but now I need a block which can change the logic value to opposite on every rising edge. So it should keep the 1 or 0 as long as edge occurs then make invertion. Is a block like this in simulink?
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