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Recent content by Jarvsiri

  1. J

    Latchup prevention using Deep Nwell

    How the use of Deep Nwell can prevent the latchup in a cmos? and how to draw layout for the same with deep nwell for cmos ?
  2. J

    [Moved]: standard cell speed dependency upon number of tracks

    Which standard cell will have more speed ,9 track standard cell or 12 track standard cell and why ?
  3. J

    Electromigration fail on Vdd track in standard cell

    I have the restriction to use only a single label on em failing track .So more m1_m2 via connections are also not possible.
  4. J

    Electromigration fail on Vdd track in standard cell

    EM is failing on vdd track metal2 in standard cell.
  5. J

    Fingering effect on analog layout and standard cell layout

    So,do we prefer fingering/folding for analog layout or not ?
  6. J

    Antenna violation problem in vlsi layout

    If there will be a case when the antenna violation is coming on millions of wires in layout, then what we will do ? As, Initally we prefer for higher metal jumper but the case is also that we don't have any left higher metal jumper and also using a reverse bias diode for millions of wires...
  7. J

    Memory layout problem in fingering and sharing

    Memory layout is a digital layout type, still sharing and fingers are not used in memory layout . why ?
  8. J

    Fingering effect on analog layout and standard cell layout

    How the use of fingers of transistors can effect the resistance, capacitance and speed of a mosfet in analog layout and standard cell layout ?
  9. J

    [SOLVED] Pmos with different potential in the same Deep Nwell Area

    Can we make a pmos inside a DNW area with different vdd potential if the same DNW area have already a VDD potential tapping?
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