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Recent content by japoliveira

  1. J

    Solution to delaying the signal in VHDL code

    Re: how to delay the signal? Hi! This is my first post in this forum :P In a CPLD you have at least two ways to delay an input signal, depending on how much time you need for that delay. The first approach you may consider is using logic cells; for a 10 ns delay 2 or 3 LCELLs are enough (for...

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