Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: how to delay the signal?
Hi! This is my first post in this forum :P
In a CPLD you have at least two ways to delay an input signal, depending on how much time you need for that delay.
The first approach you may consider is using logic cells; for a 10 ns delay 2 or 3 LCELLs are enough (for...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.