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thank you bro ,i whant achieve :
when the sequence "1101" by using the input a switch is detected then y=1 until rset =1 (when rset =1 than fsm come to state 1)
that is my new code
library ieee;
use ieee.std_logic_1164.all;
entity machine is
port(
rst,clk,a : in std_logic;
y : out std_logic);
end machine;
architecture arc of machine is
type m_state is (s1,s2,s3,s4,s5);
signal state : m_state :=s1;
begin
process(clk,rst) is
begin
if...
thank you , i will try it now ,
but bro i have a question , consider the input a is switch , so if the switch is closed , maybe the fsm can read 11111 when the switch is not changing fast lik the clock
any help ?
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Akanimo i have used your correction , it work in simulation ...
hello , i try to make a fsm with a reset and one bit input a and output y to detect the sequence "1101"
i code it with vhdl and simulite it but it dont work
please help me thank you
library ieee;
use ieee.std_logic_1164.all;
entity machine is
port(
rst,clk,a : in std_logic;
y : out...
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