Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello All,
i am using cadence 16.0 tool for PCB Designing.when i tried to route the components which are connected in parallel the nets are taking the shortest path instead of what the sequence followed in capture.i mean if we r connected fr0m R1-R2-R3.if we drag R3 close to R1 it...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.