Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Can anyone clarify what is the expected behavior of the ERROR response when coupled with the hreadyin signal?
Can first cycle of ERROR response (Cycle0 with hresp = 1 and hreadyout = 0) be provided when hreadyin = 0? What about second cycle? If hreadyin = 0 during second cycle of ERROR...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.