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Recent content by jai_mahankudeda

  1. J

    About multi stage clock gating

    Hi, Please can anyone share what is avg, multi stage clock gating and avg. multistage fanout in Synopsys DC in detail. These two are calculated after multi stage clock gating. Thanks in advance, Jai M
  2. J

    How to include generate name with instance in RC

    Hello, Please help me out on this, In my RTL code I have a generate statement generate if (SYNTH == 1'b0) begin : g_SIE SIE i_SIE( ); During elaboration DC adds this generate name as a prefix to the instance name, DC: A_instance/B_Instance/g_SIE.i_SIE/INST0 but RC doesn’t use...
  3. J

    Equivalent command of update_lib

    Hello, I want equivalent command "update_lib" of Synopsys DC in RTL compiler. Thanks in advance.
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