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Recent content by jai5605

  1. J

    [SOLVED] Verilog Programming problem

    I solved it on my own, but thanks a lot anyway! you're right. w[8] was the problem.
  2. J

    [SOLVED] Verilog Programming problem

    `timescale 100ns/1ps module CarryLAS_tb; reg [7:0] a; reg [7:0] b; reg ci; wire [7:0] sum; wire of; //overflow wire co; integer i; CarryLAS_8 CLA(a,b,ci,sum,co,of); initial begin a=0; b=0; ci=0; end initial begin // all possible cases for(i=0; i<262144; i=i+1) // 2^18 #10 {a...
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