Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I know a little about MBIST:
model_name_bist.v ----- the bist controller
model_name_bsit_con.v ----- the bist controller and ram_block (which include bist controller and ram_bypass block)
model_name_tb.v -----TB
model_name_v.dcscript -----DC script ,which can synthesis...
asynchronous FIFO
Thank you ,radix.
You're right ! The asynchronous FIFO in my design has a rd_count which indicate the number left in fifo. At the worst case the rd_count is delayed one read clock period than normal. I think this is unavoidable.
Hi ,all.
I have a asynchronous FIFO in my design, I found the simulation results is different between RTL and netlist. It is caused by the asynchronous FIFO, at the mistake time, the read clock and the write clock is very close(0.5ns), the netlist output is late than the RTL output.
I wonder to...
I need write a 512 point FFT in Verilog, I want use radix-2 first , divide 512 to two parts of 256 points, and then use radix-4 to calculate each 256 points. In the end ,after the final Butterfly ,it need binary re-order . I would like to know How to re-order the result? Is it different as...
Can I use radix-2 first , divide 512 to two parts of 256 points, and then use radix-4 to calculate each 256 points. How to re-order the result ,is it different as normal ?(binary re-order)
Thanks in advance
Hello all!
my formality is ok in : RTL <-> DC1 net( first dc net)
RTL <-> mbist net
RTL <-> DFT net, DFT net <-> DC2 (final net)
but RTL </> DC2 (final net) is verify failed
I use debug to analysis , found its due to...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
