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0.18um technology,gpdk 180nm, normal capacitors n resistors.How to draw the layouts for this. while extracting layout from schematic only the nmos's are extracted not the res n cap.
thank you
hi, i m drawing the gilbert mixer layout in cadence, where can i find the design rules? and how to draw layout for passive components resistors, capacitors in cadence? plz halp me out in this,its urgent........
i designing a balun in cadence, for converting differential inputs to single input,for that i have to maintain 50 ohms single input impedance and balanced output impedance is 50ohms, how can i design the balun with these requrements, plz tell me if u have the solution its urgent.
can i use the...
hi,i m doing the mixer simulations,for that i need to insert the balun model,i m using cadence,spectre simulator where can i find this???????? plz help me out
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what is meant by this symbol (:=) , and tha (alias) siganal in VHDL and how to convert this into verilog plz help me,AND GIV ME REPLY AS SOON AS POS.........................
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