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Recent content by iwpia50s

  1. I

    [Asynch Reset] Find active low or active high

    If you can you trace the path from the reset port to the reset pin on the sequential cell then the logic unateness will show you.
  2. I

    standard cell placement using Cadence SoC Encounter

    Looks tome like your LEF library doesn't match your timing library or your Verilog netlist
  3. I

    can a register have z as its value?

    I suppose one could design anything, but it practice, a register is almost never a "Z". Even in power switching designs you would use retention.
  4. I

    [DFT] Should the Spare Gates be included in the Scan Chains?

    Spare flops are usually not included in scan chains, the D pin is usually tied low. You may want to have the clock pin connected to a clock but in some cases you want the clock pin tied off as well. You should have some spare flops in each clock domain so the flop load is already accounted for...
  5. I

    effect of Clock Uncertainity

    Hold uncertainty is smaller also because you're using the fast corner for timing so the delays are shorter.
  6. I

    Need help in writing a tcl script to find out cells in the clock path

    When asking a question like this it helps to know the tool you are using because each tool has its own way of tagging cells.
  7. I

    encounter timing optdesign

    While you can fix input2reg hold violations at the block level, it is better to get the top level timing so you know your violations are real.
  8. I

    route_opt not routed to closest signal pins

    What are your max_tran, max_delay, max_cap settings?
  9. I

    Crash in Synopsys tools, why?

    The first thing I would try is to make sure I'm using the "-64" for 64 bit switch.
  10. I

    High speed sine wave to square wave converter

    A simple comparator should do the trick. otherwise you could get fancy and use a pulse width modulator.
  11. I

    How to convert the db file gtech.db to gtech.v format?

    Re: db format to verilog Shurik is correct, however, the output verilog will be in gtech library.
  12. I

    Problem with net instantiation

    Looks like you did not declare them as a signal.
  13. I

    distribute spares in placement

    What tool are you using?
  14. I

    Need help with problem involving voltage and current sources and resistors.

    One of the first things taught in engineering school is correct, neat writing...at least when I was in school. I can't read it.
  15. I

    Newb alert - looking for some 101 pointers

    No matter which type of design you do transmission line theory will go a long way.
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