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Recent content by ivlsi

  1. ivlsi

    [QuestaSim] How to reload design after re-compilation?

    Hi All, How is it possible to re-load / re-elaborate the design after its re-compilation (without starting the simulation)? If I'm using the vsim command, all the windows are closed and then reopened (including the Wave window with the signals). So, is it possible to re-elaborate the design...
  2. ivlsi

    Automatic Gated Clock

    1) In what cases the clock gating should be done manually? I know BackEnd tools insert the clock gating on the outputs of the PLLs. Are there more cases where the gated clock should be inserted manually? 2) It's clear that gating a single flop doesn't have a sense. So, what's minimum flop...
  3. ivlsi

    Automatic Gated Clock

    OK, besides the min number of flops, what other configurations could be done for the clock gating insertion by tools (e.g. synthesizer)?
  4. ivlsi

    Automatic Gated Clock

    I'm talking about the Automatic Gated Clock, which is inserted during the synthesis....
  5. ivlsi

    How to compile C-Model to my TestBench?

    Hello, I have a C-model (code written in C-Language). How can I compile it to my TestBench? Thank you!
  6. ivlsi

    RTL HandOff - what includes?

    Are there any additional checkpoints for the RTL delivery?
  7. ivlsi

    RTL HandOff - what includes?

    Hi All, What's the Handoff for RTL delivery to Verification and BackEnd groups? As I know, it's as follows: 1) level-0 verification by direct testing (TestBench) 2) Running Lint on RTL 3) Running SpyGlass on RTL (CDC checks) 4) providing constraint files for the synthesis What's else...
  8. ivlsi

    Automatic Gated Clock

    Hi All, How the Automatic Gated Clock should be inserted into the flow? Should I prepare the RTL code in some way for the Automatic Clock Gating? In what cases it doesn't worth inserting the Automatic Gated Clock? How could the Automatic Clock Gating be managed? Thanks!
  9. ivlsi

    Gated Clock: why using of Latch is preferred over using a FlipFlop

    Hi All, As for the Gated Clock, why is Latch preferable over Flop for gating the clock? Thank you!
  10. ivlsi

    Single Reset in Async FIFO - how to use? What clock domain connect to?

    what's going on when there is a removal/recovery violation? how to solve in FPGA? ASIC?
  11. ivlsi

    Single Reset in Async FIFO - how to use? What clock domain connect to?

    I can choose the flops type ... For FIFO itself I have chosen FlipFlops without reset. As for the around logic - FlipFlops with the reset. But there is only one reset pin but two clock domains... So, if I want to synchronize the reset, so for which clock domain? write side? read side? slowest...
  12. ivlsi

    Single Reset in Async FIFO - how to use? What clock domain connect to?

    "properly designed flip flop can do this for you" - the timing of clock and reset is defined externally to the flop... so how could it handle internally? the clock & reset can rise/fall close one to another, so removal/recovery violations may happen. What is crosscheck? could you explain, please?
  13. ivlsi

    Clock Gating -> when it's worth to insert it manually?

    Hi All, When it's worth to insert Gated Clock manually in the Code or during BackEnd? What cases are not covered by the Automatic Clock Insertion? Thank you!
  14. ivlsi

    Single Reset in Async FIFO - how to use? What clock domain connect to?

    should the clocks be gated so they will start after de-assertion of the reset in order to eliminate the metability? As for as I know, using the async reset may bring to the logical errors ... So, how to use the async reset on the safe side? stop the clocks during the reset?
  15. ivlsi

    Single Reset in Async FIFO - how to use? What clock domain connect to?

    Hi All, An Async FIFO has two clocks, but a single reset. Where/how to connect this single reset (what clock domain)? Is a single reset enough? Thank you!
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