Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by ivb1991

  1. I

    AXI master and slave with different clocks

    1. Now I think that "single" means that master interface uses ONE clock signal, and slave interface uses ONE clock signal, but this clocks can be different. In spec there is no phrase about that master and slave must always operate at same clock signal. 2. If it's not mentioned anything about...
  2. I

    AXI master and slave with different clocks

    The answer to the first question is Yes. I didn't understand clearly the second question. The AXI2AXI bridge has two interfaces - slave interface(SI) and master interface(MI). SI of the bridge must be connected to your master, and MI of the bridge must be connected to your slave.
  3. I

    AXI master and slave with different clocks

    I don't think that this RTL is free)) You can buy it(crypted) or write yourself, or try to search in web) Yes. As I already said(twice by the way), master and slave clocks are defined by you, not the protocol version))
  4. I

    AXI master and slave with different clocks

    I think "single" in this case means "not differential". Docs are written by humans, and could contain mistakes and ambiguities. As I said, on which clocks will operate master and slave depends on designer.
  5. I

    AXI master and slave with different clocks

    sun_ray, example of async AXI bridge from ARM(pdf download is available): http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dto0023b/index.html
  6. I

    AXI master and slave with different clocks

    Wrong. It's not forbidden to set different clocks for master and slave.
  7. I

    CDC for AXI master and AXI slave

    sun_ray, see my reply in other thread: https://www.edaboard.com/threads/312407/#post1338172
  8. I

    AXI master and slave with different clocks

    Of course AXI master and slave can operate on different clocks(with different frequencies and/or phases). Such situation is common in large designs like SoC, and called "clock domain crossing"(CDC). In case of AXI it's necessary to implement AXI2AXI asynchronous bridge.
  9. I

    Why do we need zero-delay netlist simulation?

    STA is not my job, but as I know constraints could be verified automatically by tools like Encounter CCD. Estimation of power consumption... it doesn't require running full regression simulation of post-layout+SDF.
  10. I

    Why do we need zero-delay netlist simulation?

    So it seems that each company have its own design flow, which may not include zero-delay netlist simulation. In our current project(in which I participate) we run regressions on zero-delay pre-layout netlist because running regression for post-layout+SDF is too long(several weeks, depends on...
  11. I

    module instantiation in verilog

    Why you don't like concatenation? It's a standard practice to use this operator in such cases.
  12. I

    Post layout simulation

    I never had to do this, but according to my understanding you have to extract delays(in SDF format) from layout and annotate them to post-layout gate-level netlist, and then perform typical simulation as for pre-layout netlist. Try to search about SDF extraction and annotation for more details.
  13. I

    Why do we need zero-delay netlist simulation?

    Heh, very good question, I sometimes wonder myself this question. I think zero-delay netlist simulation is needed just for reassurance, because formal-verification tools not always behave correctly(I often face with mapping problems, and false nonequivalences), as well as synthesis tools. Also...
  14. I

    [SOLVED] Advantage of AXI over AHB

    AXI is mush faster than AHB, due to full-dulplex architecture (independent read and write channels, also independent address channels), and some other features. AXI usually operates at higher clock frequency than AHB. Refer to specs from ARM site for detail.
  15. I

    Realization of inout after synthesis

    Bidirectional buffer from library.

Part and Inventory Search

Back
Top