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Recent content by itsmevivekagrawal

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    VLSI, Verilog Jobs in India

    I am currently working on Aakash Tablet PC in IIT Rajasthan. I have more than 1 year experience in VLSI, verilog, FPGA Design & multi layer PCB design. Please tell me any opportunities in India regarding this domain. Vivek Agrawal
  2. I

    Regarding PCB Foot print Design

    Dear I am working on eight layer PCB but I am getting some crucial problem to design a BGA array footprint Please send me any BGA foot print Thanks Vivek Agrawal
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    Orcad warning[ORCAP 36006]

    Hello Dear, I am getting this error in orcad 16.0 while I am generating a net list #1 WARNING(ORCAP-36006): Part Name "ANT IC_0_WIFI_ANTEENA_F=2400~2500MHZ" is renamed to "ANT IC_0_WIFI_ANTEENA_F=2400~25". please tell me How to solve this problem Thanks

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