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Recent content by itmr

  1. I

    associate handels in matlab GUI

    Hi I am Itamar and i have some problem while using MATLAB GUIDE. I need to update multiple text boxes from UART Received data. i created 'ByteAvailabeFcn' that interrupt when getting the configured num of bytes from the UART. When i created the interrupted function that suppose to read the...
  2. I

    8bit 10bit encoding mode

    Hi can somebody can explain me (or linked me) whats the effective of this encoding mode? i understand that this encoding mode make an equal amount of zeros and ones in a word - but i cant understand why it is good for... i mean whats this DC Balance good for? thank a lot Itamar
  3. I

    Chipscope i/o set/reset

    HI ALL For those who used VIO core using chipscope i have some questions-- 1- i running VIO using the old fashion way - generate ILA,ICON,AND VIO and connect them - there is any new way to do so from the .cdc file creating? 2 - i can toggle FPGA I/O directly or i can toggle just internal...
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    Question about cutting bits in fixed point FIR

    Hi ALL in now days i design FIXED POINT FIR that wil be implemented on FPGA the filtering unit using cic decimation followed by 2 fir LPF. the input to the unit is 32 bits - 30 fractions and 2 for real number. the end of the unit in 57 bits and i take just the fractions -51 downto 22. when...
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    load bin file to matlab

    Hi All i have some issue to solve and i will be very happy for yours help i have 3k vector 12 bit each in txt file . - i want to load it to maatlab and make any manipulation ( compare it with some filter output filters. does someone have any idea. when i load it to matlab i get decimal number -...
  6. I

    MODELSIM gate level simulation problem

    hi i am trying to simulate my design post synthesis with modelsim i generate the netgen folder after " generate post synthesis simulation model " and " generate place & route post simulation model" i suppose to get delay file - SDF AM I RIGHT? now when i open new project in modelsim and add...
  7. I

    resource sharing in MATLAB HDL CODER

    OK TrickyDicky - but after the designed the tool suppose to aplly the sharing factor and if there any mistake in my design i will get some error - any case one of my filters taken from the simulink cores and i just enter the coefficient i calculate - so it mean that the tool suppose to support...
  8. I

    resource sharing in MATLAB HDL CODER

    hi what do you mean? if i designed FIR with the basic matlab function i shouldnf use resorce sharing option for HDL CODER? i mean the tool doesnt automatic recognize my design? and after my resource sharing configuration the tool automatic share the repeated sections? the matlab demo shows...
  9. I

    resource sharing in MATLAB HDL CODER

    hi all i am itamar. E i designed FIR in MATLAB and i want to generate HDL CODE USING MATLAB HDL CODER . my version support only simulink hdl coder but i know the the newest version support generate HDL directly from matlab code with resorce sharing option. - that method reduce area. does sombody...
  10. I

    Cic decimation filter resolution

    hi all i design now decimation unit to downsample signal samplesd in 1M to 2K i cascaded cic decimation then fir decimation and then downsample block ( in simulink). when i simulate the unit it looks good - i mean i can see the filter gain ( when the input is pulse) and i see the down...
  11. I

    inout to input ports connections

    Hi all One of tbe solution that i found is to direct the data throught tristate buffers ( others => 'z') I will attach the code later
  12. I

    inout to input ports connections

    thank u all i solved the problem - it looks good - synthesis and simulation looks good to i will explain later and attach my code
  13. I

    inout to input ports connections

    its system demand to synchronize the rd_en and the _w_en and as well to synchronize the oe. but i will try to leave the oe doesnt synchronize with the system and maybe start the ips processes earlier and valid the to the gdata earlier...i will think about it thank you
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    inout to input ports connections

  15. I

    inout to input ports connections

    yes you right - i got the error when direct mapping and when i solve the error with the enable 2 clock delay inserts. now i plan to have just 2 clocks delay and got 4 probably... thats my problem ---------- Post added at 09:23 ---------- Previous post was at 09:19 ---------- hi i am sorry...
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