Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
dd2 burst length
Thanks maksya!
You are right.
"If RDQS is disabled, DQS0-DQS17 bacome DM0-DM8 and DQS9#-DQS17# are not used." This description is found in HTF9C32_64_128x72 datasheet. And in the functional blcok diagram the DM is not connected to Vss also.
But, i am not sure if HTJ36C512x72G...
burst length4 in ddr2
If it is a component, DM is a good choice.But as i know, in DIMM package, DM is usually connected to VSS by mannufacture. Such as HTJ36C512x72G from micron.
:cry:
Added after 11 minutes:
You mean i can store a 4/8xbus_width data first, and then wirte them in one write...
ddr2 burst
Hi,everyone
I want to write a ddr2 controller in VHDL.
Now, there is a problem in front of me.It is burst length.
In JEDEC standard its value is 4 or 8. when it's 4, it means if you write a data in location0 the location 1,2,3 in the same columne will be assert one by one.The data...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.