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Recent content by irun2

  1. I

    which constraints will affect the clock spec generation in CTS?

    Hi all, Can any one tell me which constraints written out by DC, like set_clock_latency/ set_clock_transition/ set_clock_uncertainty, will affect the clock spec generation in CTS stage? The generated Clock.ctstch looks like below: AutoCTSRootPin clkgen_m/u6/Z Period 40ns...
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    Can we call I2C is self-clocked?

    Thank you for the explaination.
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    Can we call I2C is self-clocked?

    Hi friends, This is confusing to me. The definition of self-clocking means the clock infomation is embedded in the data transmission. From this view I2C is not self-clocked as there's a clock SCL running alongside the data. But recently I've read "self-clocked I2C" in the functional block in a...
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    What does "*" mean in Encounter 's postRoute.slk report

    Hi friends! In the timingReports directory there's **_postRoute.slk, and in this slk file it looks like below: # Format: clock timeReq slackR/slackF setupR/setupF instName/pinName # cycle(s) exck_i(R)->exck_i(R) 15.000 8.153/* 5.000/* ex_rd_o 1...
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    How to put constraints on latch-based design?

    Dear all, Is it possible to synthesize & verify a RTL latch-based design using DC? Or for latch-based designs, there're methodologies rather than DC? I know there's a way to create two non-overlapping clocks using create_clock, but not sure if DC/PT can verify the timing after PR, that the...
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    [SOLVED] How to instruct DC to correctly check the timing of a two-edges design?

    Thanks a lot, I'll give it a try:)
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    [SOLVED] How to instruct DC to correctly check the timing of a two-edges design?

    Hi matter, But I think DC has got the wrong hold relationship, It should not check the hold on 0ns of the launch edge, it should have been check the next rising edge, that is 20ns. 20+0.108-10=10.108. The question is how can I put constaints to let DC check the correct hold relationship?
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    [SOLVED] How to instruct DC to correctly check the timing of a two-edges design?

    I have a design that has to used both rising and falling edges of a clock, to improve the holdtime margin. But I found DC has problem when doing timing analyze. The hold time report looks like below. The clock period is 20ns, and I think the correct hold time slack should be 10ns+0.108=...
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    How to let DC create the view_command.log file?

    I've checked the .synopsys_dc.setup file, even the variable view_command_log_file is set, DC does not create the file name specified. Is that bacause "view_command_log_file" is only in effect in Design Analyzer, and not avaiable to dc_shell-t or Design Vision?
  10. I

    ECO compiler is no longer exist?

    I'm working with DC2007.03, today I've found that the eco_align_design is a "unknown command". But I still could set the variables eco_instance_name_prefix, compile_instance_name_prefix. Does anyone knows from what version on, Synopsys begins not to support ECO compiler? And why? Thanks in advance!
  11. I

    How to do formal verification on a retiming netlist and rtl?

    As this is for test purpose only, I haven't put any constraint on it. read_verilog mul16x16.v current_design mul16x16 compile pipeline_design -stages 3 -clock clk -asyn rst write_file -f verilog -h -o mul16x16.vg
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    How to do formal verification on a retiming netlist and rtl?

    Analyzed log RTL module mul16x16(clk, rst, opa, opb, alu_out); input clk, rst; input [15:0] opa, opb; output [32:0] alu_out; assign alu_out= opa* opb; endmodule GATE module mul16x16_DW_mult_uns_1 ( a, b, product, clk, rst ); input [15:0] a; input [15:0] b; output [31:0] product...
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    How to do formal verification on a retiming netlist and rtl?

    Oops...The code was in my home computer...I will attach them tomorrow. To answer your questions, the RTL is purely combinational, but as it's retimed by pipeline_design, the gate netlist has comb+ seq. Design Compiler was used for logic synthess.
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    How to do formal verification on a retiming netlist and rtl?

    Hi all, It's a simple 16x16 multiplier and it's used for test only. After first compile I used the command pipeline_design to retime that mul. And a default.svf was created. In formality environment, I imported the svf file and rtl, db library, and gate netlist, and set top module...
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    Does SOC Encounter ECO Post-Mask flow support this kind of netlist changes?

    Hi everyone, I am fresh to SOC ECO and need help on it. Thanks! The chip has been taped-out and after some tests bugs are found. I’ve modified the verilog netlist using several spare cells. The changes are like below: TOP module originally has instance of module A and module B, now signals...
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