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Recent content by irontitan76

  1. I

    VHDL: Register File with Eight 8-bit Registers

    library ieee; use ieee.std_logic_1164.all; entity regfile is generic ( dw : natural := 8; size : natural := 8; adrw : natural := 3); port ( A : out std_logic_vector(dw-1 downto 0); B : out std_logic_vector(dw-1 downto 0); C : in...
  2. I

    VHDL: Register File with Eight 8-bit Registers

    Okay, hmm. I used the case statements to eventually determine which address to use. How would the "regArray( to_interger(unsigned(A_adr))) <= something;" help do that? Furthermore, how would I use logic to determine the address to use? That's what I thought the 3 bit address input was for. I got...
  3. I

    VHDL: Register File with Eight 8-bit Registers

    Would it be something like this? Or am I totally going about this all wrong? I'm sorry for the trouble. I just need to get this done. I learn by examples and I haven't gotten many in class. I've tried to look up information on VHDL online, but it hasn't helped out entirely. library ieee; use...
  4. I

    VHDL: Register File with Eight 8-bit Registers

    Thanks for the reply. And yes, that's what I thought as well, but I really am a beginner in VHDL and have no idea how to start.
  5. I

    VHDL: Register File with Eight 8-bit Registers

    Hi, I am desperately trying to figure out an assignment using VHDL. As of right now, I don't have much of an idea of how to start. I know other programming languages, but VHDL is, of course, more coding instead of programming. To me, VHDL seems somewhat illogical. Nonetheless, I am trying to...
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