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I realized that one solution is to have two PLL blocks (I tried one that goes from 50 to 40Mhz) and the other goes to my target frequency. Quartus is giving me some pains though ... it doesn't like that the input of the second PLL is coming directly from the first PLL. Hmm...
Hi,
I'm trying to generate a 193.16 Mhz clock using PLL for a particular VGA resolution (1920x1200@60Hz). I understand that this can be generated from a 50Mhz oscillator (that my board happens to have) using the following multiplier/divisor: 4829/1250. My version of Quartus (12.0 .. need old...
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