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Recent content by ipcore

  1. I

    PCI bus interface question about signaling voltage

    PCI bus interface pls reference IDT QS3861
  2. I

    HELP: Can't download *.pof file to my chip! (Altera CPLD)

    HELP: Can't download *.pof file to my chip! (@ltera CPLD) I think the Noise on TDO is too much that Jtag can't read the JTAG ID
  3. I

    How to name/distinguish layers in Orcad Layout Plus ?

    layer definitions u can create 3 types gound by split plane,but u can't derfine 3 names
  4. I

    what is the meaning of "biasing"

    It means a basic voltage for curcirt
  5. I

    Where to study issues related to Ethernet Phy design?

    Ethernet Phy Design now PHY use digital and DSP technology like a soft radio princple
  6. I

    Help me understand Counters

    Counters based on the time interival you need 2^n
  7. I

    internal clock generation

    It's for function simulation only,can't be use for generate clock
  8. I

    did C@dence PSD for linux include Orcad?

    Did C@dence PSD for linux include Orcad?
  9. I

    Altera Nios Discussion Board

    https://www.niosforum.com
  10. I

    IC design lission from Berkeley

    **broken link removed**
  11. I

    I need help with HFSS 9.0

    It has a training cource in website
  12. I

    Why Allegro has very few libraries ?

    allegro library .... CD3 is library for ConceptHDL,not package library

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