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Recent content by inputoutput

  1. I

    Worst negative slack increases during post-CTS

    No, it's just one corner. I'm getting lots of violations during nanoroute though, I don't know if that plays a role...
  2. I

    Worst negative slack increases during post-CTS

    I am doing a post-CTS timing optimization in Encounter. During the optimization the summary report is something as follows: WNS (ns) -3.751 TNS (ns) -26643.7 Violating Paths: 21986 All Paths: 67386 However, after optimization is complete, timing actually gets much worse: WNS (ns) -23.290 TNS...
  3. I

    Power optimization commands in design compiler

    I am using design compiler version 2015. It seems the commands set_max_dynamic_power and set_max_leakage_power are no longer recognized. I get the following warning Information: Command 'set_max_leakage_power' is obsolete and is being ignored. (INFO-102) What are the equivalent commands to use?
  4. I

    Unsynthesizable verilog code

    What errors are you getting? Have you verified the path to your target library is correct?
  5. I

    DRC Violations in Encounter

    These violations are reported after CTS. Any idea what they could mean? Where do I begin? There are more than 1000 of these violations.
  6. I

    DRC Violations in Encounter

    Yes, the errors occur after nanoroute. But I now notice that the violations started after CTS. There are no violations after placement. Any ideas why CTS could be causing violations?
  7. I

    DRC Violations in Encounter

    After running nanoroute in Encounter I get the following message The violations are due to spacing. During route I get the following warning, I don't know if it's a reason for the problem I have done place and route for other designs using this same library without much problems. I don't...
  8. I

    Floor Plan Row Spacing

    Thanks Sam (can I call you that?). Yes, I do mean "row spacing". You find this setting when you go to specify floor plan > advanced settings. Thanks.
  9. I

    Floor Plan Row Spacing

    Is there any rule that determines row spacing in Cadence Encounter floor planning? I have done place and route with and without specifying the row spacing, and sometimes get routing violations. What is the rule of thumb?
  10. I

    $recovery error in post-synthesis simulation

    The problem was the asynchronous reset wasn't properly synchronized with my flip flops causing recovery errors. This works well now at the given frequency. Thanks for all the help!
  11. I

    read_lib_saif command in modelsim

    I get the following error "System task or function '$read_lib_saif' is not defined." in modelsim when trying to read forward SAIF from design compiler. I believe this task works in VCS. Is there any substitute in Modelsim?
  12. I

    Preserving net naming in Synthesis using DC

    Do you have the code and the synthesis scripts? Does the circuit work if you modify the test bench this way: Confirm the circuit works with this change. If this doesn't work, then you have a bigger problem.
  13. I

    $recovery error in post-synthesis simulation

    Yes, I do get a "Scheduled event on delay net was cancelled." warning at 100 MHz. The design shows some output and some X's as well at 100 MHz even though the outputs are incorrect.
  14. I

    $recovery error in post-synthesis simulation

    I think I was getting the error because I accidentally had hdlin_ff_always_sync_set_reset set to true although I was using an asynchronous reset. Setting this to false appears to fix the problem. However I have another problem. The design is only working 100% correctly with a very low frequency...
  15. I

    storing values in array

    What do you mean by the values are overlapping? What output are you getting, what output are you expecting to get?
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