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Hi All,
I am new to synthesis. I am working on dc compiler. I am trying to do bottom up synthesis .
I have 5 modules, addr, muxsel, counter_dec, counter_inc and top module.
what i know is that, we have to compile all modules individually and then top level.
The design is very basic, just to...
Thanks klausst.
But i still have doubt. The question is basic inverter analysis.
When the Vdd is off and we apply input the inveter, the output is X. But how it goes to X.
Can anybody explain??
Hi all,
I have two questions regarding CMOS inverter output.
1) When the Vdd is off and my input to inverter is still present (0 or 1). what is the output.
I think it gives X, but dont know how.
2) When Vdd is applied but my input is X. In this scenario what is the output?
Please help...
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