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Recent content by indranilh

  1. I

    How to verify the output of xilinx in matlab

    or u can do one thing save the output file in text format from any logic simulator and then read that text file in the matlab. den ur purpose will be solved.
  2. I

    Regarding error in running vhdl program in synopsys vcs

    vcs running vhdl here is the script to run vhdl file in vcs Added after 2 minutes: here is the vcs command for vhdl
  3. I

    CADENCE ENCOUNTER Design File

    you can download the SOC design file whic i have posted earlier and after that try this file with cadence encounter.please give me your valuable comment.
  4. I

    SOC Design file( with tech file)

    here is the soc design file with the libary and tech file.please reply me your valuable comment.
  5. I

    CADENCE ENCOUNTER TUTORIAL

    cadence encounter tutorial Here is the cadence tutorial.please reply me your valuable comment.
  6. I

    Floating Point Representation in Hardware

    you can convert this to as a fixed point number by multiplying it with the no of 2's power.i mean to say multiply .707 with 1024(2^10).
  7. I

    Please help me......................

    yes it is possible.you can use seamless fpga tool of mentor graphics or Xilinx edk also do the same.or you can choose coware tool for this.
  8. I

    Need the solution manual to VLSI for Digital Signal Processing by K K Parhi

    is there any one having of the solution of VLSI for Digital signapl precessing ,K K Parhi's book.I have an exam on this paper.so please help me.
  9. I

    any one working on software radio

    is there any one working on software radio? then plz reply to me.
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