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Recent content by incisive

  1. I

    master Interface address mapping

    suppose in an SOC's address mapping will the master interface or master(processor) will have the address decoding according to the system?? thanks & Regards
  2. I

    What are differences between ASIC and SOC ?

    Re: ASIC vs SOC SoCs can be fabricated by several technologies, including: Full-custom Standard cell FPGA SoC designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. And with fewer packages in the system, assembly costs...
  3. I

    any docs regarding Bus Functionality Model or an example illustrating it

    Re: Any docs regarding BFM........plz Hi Guru, suppose AHB(AMBA BFM) u need to write all the transactions as test case's so that it acts as bus to verify the slave/master interfaces.
  4. I

    tcl query for regular expression

    Thank you microe_victor, Even i found out a simple expression which changes the given value accordingly. i.e regsub {\[3:0\]} $sample3 {[7:0]} sample5 well thanks again!!
  5. I

    tcl query for regular expression

    tcl regular expressions Hello all, suppose i need to search atom from a group of lines from a file, for example file is item list atom [3:0] grant; ready here i need to change the 3rd line from "atom [3:0] grant" to "atom [7:0] grant" what is the necessary regular expression to do the...
  6. I

    Design rule constrains set_max_transition and set_max_capac

    set_max_transition Typical Design rule constrains are Set_max_fanout and set_max_transition or Set_max_fanout and set_max_capacitance or But not both i.e set_max_transition and set_max_capacitance. Why is this. Can any one please explain? Thanks & Regards Added after 5 hours 44 minutes...
  7. I

    Comparison of Perl and Tcl script languages

    tcl synopsys there is no direct comparision betw perl & tcl, perl is used to find/replace/substitue any of the patterns in the file in the design flow. tcl tool cmd lang, is used to control the tool, or can be used to pop out graphics window with radio buttons and other features for the...
  8. I

    What is low power vlsi design

    Optimization Method Power-Saving Percentage Algorithm Level 75% Architecture Level 50%–75% Register Transfer Level 15%–50% Gate Level 5%–15% Transistor Level 3%–5% PDynamic = 1/2.n.B.C.Vdd.Vdd.F various factors involved in saving dynamic power ß Saves power by optimizing the...
  9. I

    Questions and answers on PIC express verification

    what is pci express loopback hello jsps, comparing USB and PCI interms of usage is impractical, both serve differently for different purpose. serial // parallel.
  10. I

    Initial Statement in Verilog: Blocking or Non Blocking

    Re: Initial Statement If the testcase/testbench is as such for Initializing DUT I/P Values initial begin a = 0; b = 0; c = 0; // Use Blocking Statements end for writing a test case initial begin @(posedge CLOCK) begin a <= 1'b1; b <= 1'b0; //...
  11. I

    What is low power vlsi design

    well there ae three levels of achieving low power RTL level architectural level algorithmic level most popular is the algorithmic level of achieving low power. there are some methods like clock gating signal gating reduting switching activity - transistor sizing, progressive...
  12. I

    What is low power vlsi design

    Low power Design : power = static + dynamic power. Dynamic power can be reduced in gate level as well as architecture/design, coding level(for small portion). example -- coding - using one-hot encoding for state machines, -- Using gate enabled clocks for ff's...
  13. I

    If 16-bit is half word then what is 64 - bit?

    Re: 64 - Bit Byte, Half Word, Word(not full word), Doube Word, Quad Word
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    Where can I find library samples compatible with Synopsys ?

    Re: Libraries may be go through the artisan library from ARM.
  15. I

    Multicycle vs Pipeline

    pipelined versus multicycle in the above multicycle path o/p comes out after 4 clk cycles as expected wrt pipeline 2 clk cycles here the through put varies.
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