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Forgive me, this concerns the analog part of the system but I am only designing the RTL code.
Does that requirement have an impact on the digital decoder?
Another difficulty I am having is finding a good paper on 1553 transceivers (in order to see the transformation of the analog...
I'm designing a 1553 decoder.
1553 bit rate = as in here : https://en.wikipedia.org/wiki/MIL-STD-1553
The bit rate is 1.0 megabit per second (1 bit per μs). The combined accuracy and long-term stability of the bit rate is only specified to be within ±0.1%; the short-term clock stability...
I am a new user of ovm (I used to work with vhdl/verilog based verification methodology)
I am trying to develop a verification environment for a design that communicates with an external adc( spi protocol: cs, sclk etc)
I have some questions:
As I need a model to emulate the behaviour of...
Now I see why it didn't work for me before (it's because I declared the procedure outside the main process where I call it and that's why I got this error "Cannot drive signal "..." from procedure)
Now it's working perfectly :
a <= '0';
Thank you all for your answers.
Is there any easier way to do that ?
I'm trying to shorten my test bench and this way I have to put all signal names in the list when calling init_fpga (it's not easy when fpga has many inputs (30 for example))
Also I have another question: is a wait statement...
Thank you for your reply.
That works if fpga needs to be initialized only once, but what about the case when I want to initialize those signals (init fpga) AGAIN after running some commands ?
like this :
a <= '1'...
I'm trying to write a test bench for a fpga as follows:
signal a : std_logic;--connected to input a of fpga
signal b : std_logic;--connected to input b of fpga
a <= '0';
b <= '0';
a <= '1'...