Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Design Compiler Warning (OPT-150)(OPT-314) break a timing loop,anyone help me?
This is my Phase Detector circuit & RTL code & RTL simulation
Then I used "Design Compiler"，Enter the instruction:write_sdf -version 2.1 -context Verilog"./gl.sdf"
The following warning appears
Then I Enter the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
