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Recent content by ikki

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    Pad generation - mentor adk pads errors

    mentor adk pads errors Dear Sir, I am trying to do pad frame generation. According to the ADK 3.1 guide book, it mentioned, "Step 3: In the ADK Library menu choose the pads to use from the appropriate library for your technology. Based on the technology, there may be different types of pads...
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    checking Overflows in IC station

    I would like to fix the overflow after auto routing ... I would like to know why do I get this message .. Note: Enter a valid value for argument: probe_extent (from: Ic/Ample/Argument 03) What argument does it need ? ... how do I enter it ? ... need help pls .. thanks
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    DRC and LVS - errors occur: 18L needed

    DRC and LVS I used calibre for DRC and there are DRC errors. I wanna know how do I fix it ? .... I mean for example it says there , 18L needed ... but i dunno how to amend it .... any tutorial for this ? thanks
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    How can I implement the parity check on uart ?

    how can I implement the parity check on uart ? i do know i can set to even or odd mode ... but where can I insert it ? how do i check number of even '1' and odd '1' ? any vhdl code for parity check ?
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    Synthesis - warnings when using Leonardo Spectrum

    Synthesis Hi there, I have some warnings which I would love to solve it when synyhesizing it using Leonardo Spectrum These are the warnings "C:/Jaz Synthesis Latest/rs232_060309/rs232_rxd.vhd",line 73: Warning, iShiftRegister is not assigned under reset; need loops to preserve its value...
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    Where can I find a VHDL UART example for testing rs232

    rs232 and uart anymore source we can get a rs232 uart ?..... both of the stated source kinda deviates from what I need
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    setup time is less than hold time,will this cause problem???

    where do we put the set_input_delay for asic flow ? ... izzit in the netlist ?
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    Performing gate level simulation

    there is no missing module i believe. I only have tb_adder.vhd , half_adder.vhd (netlist) and half_adder.sdf I cant find the generic signal that it popped as error.
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    Performing gate level simulation

    vsim-sdf-3240 hi there, i wanna do a gate level simulation on my design after synthesis using lenardo spectrum. I generated .vhd and .sdf file from leonardo spectrum. Can some one guide me on how to do the simulation using modelsim se ? I tried to compile it but it seems that im missing some...
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    setup time is less than hold time,will this cause problem???

    Re: setup time is less than hold time,will this cause proble if there is problem for asic flow, then how do we fix the timing ? .. how do we adjust it ? ..
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    RS-232 Receiver and Transmitter Design in VHDL

    vhdl for rs232 do i set a signal with witdth of 9 downto 0 ? or should i use 8 downto 0 and send '1' to Txd line when the count reaches 9 ? ..
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    RS-232 Receiver and Transmitter Design in VHDL

    vhdl rs232 code Thanks for the link ... Im just wondering how do i come out with the state machine for transmission part of the RS232 UART ? ... any guide to follow ? ..
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    RS-232 Receiver and Transmitter Design in VHDL

    rs232 receiver vhdl Erm, just wondering does anyone have the architecture/ block diagram of a RS232 bus controller ? ..
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    RS-232 Receiver and Transmitter Design in VHDL

    vhdl rs232 uart thanks for your reply, i searched opencores.org ... however i dont see rs232 UART project there. Actually there is one but it is not the one im finding... for this forum i searched thru too, ... but i didnt find anything matches my likings >.<
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    RS-232 Receiver and Transmitter Design in VHDL

    rs232 vhdl hi there, Im just wondering where I can get the VHDL code for Rs-232 receiver and transmitter design ? ... Im planning to use this code to implement on Xilinx spartan 3 FPGA.. Added after 59 seconds: pls send file to my email at jasperng10@gmail.com thanks
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