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If you're talking about pre-loading the internal Block RAM of FPGA, maybe this will help.
**broken link removed**
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These will help you implement the use of distributed block RAM in the FPGA, which can be used in many ways, including pre-loaded memory as you want.
Re: Block Rams
The reset value of the full flag can be set by LogiCore FIFO Generator. (see attached pic)
The FIFO full flag can come up from reset as "full" even though you have no data in it.
I'm not sure why they have this feature. I had this bug once.
Your clock and count calculations look ok.
How about your hyperterminal port settings?
I usually use
data bits = 8
parity = none
stop bits = 1
flow control = none
usb fpga fx2
martingn,
I design the firmware base on the framework provided by Cypress on Keil compiler.
I develop the application software on Visual C++ using the CyAPI driver from Cypress also.
My project is to get huge amount of data from DDR2->FPGA->FX2->PC continuously. It took me a while...
fpga jtag fx2
I have the Cypress EZ-USB on my desk now. I use it to transfer data between Xilinx Spartan-3E FPGA & PC. It is not very simple to use. Try to use their GPIF for maximum throughput.
Using this IC to program the FPGA is my next plan.
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