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Yes, u can. firstly, if the 2 i/o standard use same vccio voltage, they can exsit in same bank. secondly, some input buffer and some differential tandards can be in one bank even if they have different VCCIO.
In short, if your assignment can pass 'I/O assignment analysis', you can configure it.
@ltera FPGA pins problem
I guess that is because your pin assignments are not suitable with your design and device. Some device limitation, such as clock pin location, oe group limitation, leads Quartus failed P&R your design.
I am wondering how the FPGA realize, not in software but hardware, the function of 'low skew rate' and 'programable I/O current'.
I guess that, for low skew rate function, FPGA adds a capacitive load on the gate of output buffer; for programable i/O current, FPGA parallel connects several...
When I design on PLL or PHY of Ethernet, I always treated AGND same as DGND, and lay a small AVCC in signal plane.
Is this method just easy to practise, or is also good for analog part?
In fact, I changed an interface board of ethernet phy,which failed to pass ethernet template. I combined...
phy analog ground
To keep digital noise from interfering with analog signals, we may seperate analog ground from digital one, and then connect them at one point or via ferrat beans.
But this way will increase ground impedence. So recently, I always combined these two grounds, especially in...
altera said QII4.0 will take more time to run a project, but the result has better timing performance.
You design should have more than one clock domain, u'd better set target clock frequency for each clock domain.
Anyway, QII is always a time-cosuming tools to run a design.
I found the book, Reuse Methodology Manual for System-on-a-Chip Designs third edition, is writed for ASIC designer.
So is it suitable for PLD designer?
Thanks.
error: (vlog-19) failed to access library
Yes. I think you are new.
The problem is that you haven't creat the work library.
If it is MS window
File-> new -> library -> (accept default setting and the library name of work) click ok.
or
use commands:
vlib work
vmap work work
There is a...
From the process point of view, it is a FPGA. However, it can complete configuration itself before end of Power-on-Reset, so it is same as CPLD in practice.
To nicolepsn:
Do u have any experiences like you said. Wonder the low temperature can prevent two bits change simultaneously in the PGA logic internal.
Regards
Ifarmer
Xilinx said she can provide mass products of 1500 in Q3, but it seems it is very difficult. And as far as I know, to control the power consumption in a acceptable level, Xilinx slow down the speed of spartan3 deliberately.
site:edaboard.com bga inductance
Tantalum can only work around or below 1MHz. For high frequency, you'd better make power and ground plane as closer as possible. And place at least one ceramic caps under the chip, NP0 dielectrics is recommended.
In my opinion, the first cap is important.:)
'A Handbook of Black Magic' is the most classic book in this field. And many IC providers or EDA software companies have Application Paper or White paper about this.
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