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Re: opamp design
Hello,
What gate voltage did you use to bias the differntial pair? You should use a gate voltage that would ensure that the diff pair devices are ON and would give enough headroom for the current source.
If you'd kindly upload the testbench and the schematic, it'd be easier...
One possible method would be using current sources at the sources of both the NMOS and the PMOS (of equal currents of course) and using the NMOS and PMOS devices to switch the currents. But this is not a simple solution as you'll need to implement a current source.
I think for simualtion purposes, your input should not be a DC source, rather a Vpulse that would step from 0 to the required supply value and get held to this value. In this case, you can accurately estimate the delay between the time of applying the DC source to the time the output would...
Hello,
From the ADE Design environment -> tools -> calculator.
From the functions -> choose "cross"
at "signal" -> write the name of signal (VT("/net010") for e.g where net010 is the net name)
at "Threshold Value" -> write the crossing (voltage) value where delay is required (usually...
Re: matching questions?
Hello,
For the LNA matching to the antenna case, you're really interested in matching to prevent reflections. If there's a mismatch between your antenna impedance and your LNA, waves can get reflected back to the antenna and radiated. This can cause interference.
fingering effect
Due to second order effects, current may not change linearly with W/L.
Sometimes the effect of the STI can cause also current to change. STI stands for Shallow Trench Isolation, which is the way used to isolate the MOS device. It's performed by removing part of the substrate...
Would you kindly upload the schematic of the op-amp itself so that we can check it.
One thing is that the signal's input is connected only to capacitors, implying that this node is floating and doesn't have a specific dc value (unless it's internally biased inside the op-amp). You shouldn't...
Well, one other way would be using cascode, but this comes at the expense of more required headroom and limited swing at the output of the first stage. The swing ,however, shouldn't be a problem if the second stage have sufficient gain.
Another thing that you should node when using cascode is...
what is overdrive voltage
When you increase the overdrive voltage by increasing the current, your gain decreases because Rds of the transistors decrease proportionally with I while gm increases proportionally with sqrt(I). To increase Rds once more, you can increase the transistors' channel...
flicker noise pmos nmos
Higher gm is preferred for gain devices, because signal (power) gain will be proprtional to gm^2, while the output noise power is proprtional to gm so the input referred noise power will be proprtional to 1/gm (i.e as gm increases input referred noise decreases).
For...
noise nmos
I think that the most popular explanation for the lower flicker noise of the PMOS is because the PMOS i s implemented into separate wells which decreases its flicker noise.
Concerning which will have lower noise, PMOS or NMOS, there's no exact answer for that question. It depends on...
Re: Foundry requirement: metal density requirement when tape
I think you can just add metal layers not connected to anything at free areas where this metal is not available till you get metal density above 30%. You can also make a script to automatically do that for you.
Re: UGF and GBW
GBW is the product of the DC gain with the 3-dB bandwidth of the amplifier.
UGF is the frequency at which the gain of the amplifier is equal to unity.
It should be noted that UGF is equal to the GBW only at the case that the amplifier acts as a single pole amplifier before the...
common mode voltage
You can apply the DC to the input transistor gates using a large resistor. The DC voltage itself can ba achieved from a stable reference as a bandgap reference.
This is almost similar to AC coupling for the input signal.
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