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wangkes9,
Question 1: The impedance seen in N towards M7 is approx. 1/gm7. If M6 and M7 are identical, the gain from the gate of M6 to the drain of M7 is -gm6/gm7 which is considered to be close to -1.
Question 2: On page 357 the author describes the effect of the pole(s) of the current...
LvW,
This was my worry as well. However, the response from walker5678 is that the operating point is good and it does NOT change when sweeping from 4 to 5V.
But again, in the interest to put this to bed completely, could you please walker5678 run a sim with the 10G resistance reduce to 10Meg...
henrywent,
Actually those caps are for compensation reasons. In their absence, the input capacitace towards the common-mode circuit creates a very low pole with the huge common-mode sensing resistors making the compensation almost imposible.
OK, got it, tahnks. Is the change gradual with VDD, or is it happening on the spot?
Also, I would suggest a DC sweep of VDD from 4.5V to 5.5V and look for changes in the biasing condition of the op-amp. I would expect to see something, if we are to belive that something is wrong with the...
At what VDD level do the AC response waveforms return to normal?
Also, can you post the "normal" magnitude and phase responses?
P.S. In case you figured it out, what was it?
Re: 8 bit ADC INL problem
Here are a couple of points:
1. How is the DNL looking at the above transitions?
2. There might be something wrong with the measurement set-up. Try increasing the settling time for instance.
3. Is the evaluation result systematic or random, meaning if you measure...
Here are two reasons:
1. Noise models not correct (probably not the case).
2. The bias circuit noise is irrelevant for the output of interest. Could be like common-mode signal for a differential output. To further test this hypothesis, run an AC sim with the input being the bias current and the...
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