Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thankyou for your reply. I have derived. Both are having same Transfer functions if all gms are same. Please see the attached. If same than what is the advantage of using four Gm blocks instead of two Gm BLOCK.
Hi
I have two different biquad circuits. Fisrt biquad shown in the attached figure is a fully differential biaquad with four gm blocks while the second figure shows a single ended biquad with two gm blocks. I want to know why in the first circuit four gm blocks are used while in second circuit...
Hi
I have designed a low frequency filter upto 500Hz. Do this low frequency require network matching? Or while testing the chip will it work without network matching directly.
Thanks
Hi
Can someone suggest any company where I can manufacture the PCB a swell as do the wire bonding of my IC chip. I have found companies designing only PCB or just doing wire bonding. I want both to be done from one place.
Thanks
Hi
I saw one figure of NMOS with current source. source source is replaced by diode connected load and in another circuit the current source is replaced by a current mirror. Which one is better. Can some one tell me the use of only diode connected load inplace of current source. (See attached...
Hi
Can someone tell me if I am simulating OTA circuit do I hav eto placea capacitor or resistor at the output or not?What would be the difference if I do not place any capacitor resistor at the output?
I tried I observed the change in the phase margin only if I place a capacitor? is there any...
Hi
I want to know why body of NMOS connected to ground instead of source in n-well process and creates body effect while PMOS is connected to source and is free from body effect?
I can say that I understand simple current mirrors fairly well, but what i do not understant is the minimum output voltage requierd for the circuit to work properly...for the transistors to be in saturation.
NMOS cascode current mirror
Vout=V(D4). Vds_sat is the saturation voltage of the...
Yes with the help of diagram I know that its similar to a single transistor (two series transistors have lenght equal to 2L) but its equal to a single transistor with respect to voltage drop. See attached diagram and link...
How can this transistor be viewed as a single transistor? I have searched different articles showing that the VDS drop across these transistors are equal to a single voltage drop as shown in figure. Can you please help me in understanding this composite transistor? Is it due to the lower...
I am not taking ratio I am taking difference between first and third harmonic. I have seen paper showing difference between third and first harmonic.
In cadence version which I am using dosent have shooting-Newton and HB-PSS option so I am just using PSS analysis
Using calculator THD gives...
I want to find the THD of fully differential amplifier. I am using cadence virtuoso. I have found three options in simulating the THD in cadence which are:
1. using PSS analysis---- I select pss analysis then got ---direct plot --- forum forum then select voltage--- I place no. of harmonics...
hello
Can some one help me in understanding the layout. I am following a video for layout design of inverter. The layout of the PMOS has two squaresi.e. one for drain and source and in the middle is the rectangle i.e. the gate but when I am taking the layout of PMOS from library it has and...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
