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Recent content by ianrox

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    Calibre PEX C+CC extraction: floating nets, simulation fails

    Hi martinnl, sorry for the late response. Ive been really preoccupied with other issues. Coming back, the netlist shows I9_reset_bar which corresponds to instance I9 in the top level. I have attached the associated figures of all the levels. I attached all the major places where reset_bar...
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    Calibre PEX C+CC extraction: floating nets, simulation fails

    Thanks for the insight. I agree with you, as the extraction seems ok. In the calibre generation menu, at the bottom, I turned on 'generate SPECTRE netlist' and that netlist also had the gate terminal connected to the 'reset_bar' net as we would expect (I9_MM3) in the figure below. Unfortunately...
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    Calibre PEX C+CC extraction: floating nets, simulation fails

    Hi Timof, Thanks for the explanation. Youre right, the pex.netlist file is always generated. I opened it to try and make sense but got a bit confused. So as reference, my reset_bar net is always floating, and the gates of M8,9 and 10 are supposed to be floating where the reset net is supposed...
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    Calibre PEX C+CC extraction: floating nets, simulation fails

    Hi martinnl, you are right. The extracted schematic for C,CC extraction has unconnected nets, but R,C,CC extraction is fine. I am using array placement from the start, for both types of extractions. I haven't ever tried to extract to a spice netlist. I am not sure how its done but I'll check that.
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    Calibre PEX C+CC extraction: floating nets, simulation fails

    Yeah, that's the weird thing. I don't change anything when going from R+C+CC to C+CC. Same file, same settings..I just select Extraction type as C+CC instead of R+C+CC. I've been stuck on this for a long time now :(
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    Calibre PEX C+CC extraction: floating nets, simulation fails

    Hi Timof, In the top level, I have attached a voltage source to the reset pin. The reset pin connects to the gate nets internally.
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    Calibre PEX C+CC extraction: floating nets, simulation fails

    Yeah, I checked that as well. Everything in the top level and in the lowest level seem to be connected properly with pins as shown in the figure. The gate of the transistor isn't floating in the schematic. There is something going wrong in the extraction I feel. Since R+C+CC works while C+CC...
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    Calibre PEX C+CC extraction: floating nets, simulation fails

    Hi Akshaay Thanks for your suggestion. That would make sense if LVS didn't pass, but LVS is always successful, regardless of with extraction I do( C+CC, or R+C+CC).
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    Calibre PEX C+CC extraction: floating nets, simulation fails

    Hi I am facing a strange issue on pex extraction. I am making a simple device and created the layout. LVS is clean. When I do a transistor level R+C+CC extraction, there is no warning and the calibre extracted simulation works as expected. However to speed simulations, when I try a C+CC...

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