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Recent content by iammedjay

  1. I

    Is it possible to assign a value to a signal in a systemverilog assertion?

    hi, I have two sequences, s1 and s2. I have a property that checks these two sequences. for example, sequence s1 req ##3 gnt; endseqence sequence s2 ack; endsequence Now I make use of a property for an assertion to check these two sequences. property p1; @(posedge clk) disable...

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