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someone told me I should use sram_clk to be enable signal and use clk to drive the sram clk. Just like pic a shows.
but I am puzzled . If there are some delay with sram_clk, the new_clk (=sram_clk && clk) will work correctly? Just like pic b shows.
now I am doubt that it is the lib cell cause the error.
the clock buffer : input ck, output c and cn, It has 2 output,therefore, the soc tell me that the buffer has 2 timing arc when cts.
And all the clock buffer has 2 output pin in lib. So the apr enginner use common buffer to do apr.
##Worst case working condition
read_sdf /direct/sh-home/kevin.sheng/design/809_i2c/layout/2006_0104_from_layout/pmp_dig_slow.sdf -type sdf_max
Warning: The SDF file is version 3.0. Current SDF-3.0
supported constructs are: REMOVAL, RECREM, RETAIN and CONDELSE. (SDF-026)
soc encounter for designers
hello joe2moon, the soc encounter doesn't recongnize the set_dont_use command.
and the set_dont_use command will not exist in the sdc file when you use write_sdc command in the design_compiler.
Added after 6 minutes:
sorry joe2moon, your method is ok.
there is a option about "toggle value",which is between 0-1 ,when analyze the power consume in soc encounter. How can we know which value should be set?
What factors should be consideration?
Thanks in advance.
verilog and alu
Error: (vsim-3033) C:/Modeltech_xe_starter/my examples/test_bench_alu_operation.v(6): Instantiation of 'alu_operaion' failed. The design unit was not found.
check your code . May you write wrong module name.