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I get the error bootloader.tool missing.
I would also like to upload it directly but as i lack the knowledge and experience on how to do that i thought the arduino would be easier but i would be thankful for any resources showing how to do so as i'm trying to run an MFRC630 chip on it.
Hi Guys wish you are having happy holidays,
I’m trying to run an Arduino code on an Atmega16A and I needed the bootloader for it. I found on Instructables a detailed description of doing that but it doesn’t work and always shows an error while burning the bootloader. I have to mention that my...
https://ww1.microchip.com/downloads/en/devicedoc/31003a.pdf
The MOSFETs of the technology i'm using having a reset as a digital input means that the smallest W/L are used
The threshold voltage is 2V
That's the clock of the MC so it gives an idea about the timing of the comparator and the...
I don't have a specific MC i have looked some datasheets but couldn't find information about the capacitance i just used a 100fF C as a guess for the capcitance of the MOSFET, i also have to consider the parasitic capacitance.
I forgot to mention that the clock is 50MHz, so the fewer the clock...
Hi, I'm using a single stage amplifier IC design as a comparator for generating a reset signal when the input voltage goes below the refrence voltage (0.7V), the input voltage is produced by a voltage divider from the voltage supply (3.3V) so i'm getting an input range from 0-0.9V.
Now i want...
well thanks for your answer i could achieve it with only 2 flipflops with the reset pulse connected to the reset pin and it just does the required. Thanks for your effort though
yea actually the problem was stopping in the "retriggering" after 2 clocks
I tried generating a set signal from the rising edge of the pulse i got and feeding it as a set signal for the "counter" which is a d-flipflop with its D connected to the Qn. The problem right now is that the counter will keep counting so i will have half the clock frequency on the output after...
I'm trying to do both variants, so i thought delaying it digitally would be easier.
I tried generating a set signal from the rising edge of the pulse i got and feeding it as a set signal for the "counter" which is a d-flipflop with its D connected to the Qn. The problem right now is that the...
i have a 50MHz clock provided so i was thinking about delaying it digitally without using any capacitors as another solution for at least 2 cycles (40ns) by using a Dflipflop as a frequency divider but this will affect both pulses, which is not desired. The provided gates in the technology are...
implementing a counter would be complicated especially that i need to delay it for only 2 clock cycles and i guess the counter would stretch both pulses?
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